TLE
0 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
0 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
0 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
TLE
40 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
RTE
0 / 50
C++20
10/10/2025
AC
50 / 50
C++20
10/10/2025
WA
43 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
WA
40 / 50
C++20
10/10/2025
WA
43 / 50
C++20
10/10/2025
WA
43 / 50
C++20
10/10/2025
WA
43 / 50
C++20
10/10/2025
WA
43 / 50
C++20
10/10/2025
WA
43 / 50
C++20
10/10/2025